Mansour H. Assaf
The next generation of integrated circuitry, featuring reconfigurability, selfrepair, fault-tolerance and self-manageability relies on chips that can effectively self-test. The paper "Fault Tolerant Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities," published in the December 2001 issue of IEEE Transactions on Instrumentation and Measurement by Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu and Wen-Ben Jone is a powerful reference for professionals who develop these new chips. The paper offers a lucid case for the importance of response data compaction, as well as an extensive overview of the various built-in self-test (BIST) methods available.</p>
A member of the IEEE and the Canadian Mathematical Society, Mansour H. Assaf's research interests include computer architecture, fault tolerant computing, system-on-chip testing and fault diagnosis in digital and analog systems. He is a research associate in the Sensing and Modeling Research Laboratory at the University of Ottawa, and pursuing a doctoral degree in electrical and computer engineering at the School of Information Technology and Engineering at the University.