Kiyoo Itoh: Difference between revisions
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== | {{Biography | ||
|Image=Itoh.jpg | |||
|Fields of study=Memory | |||
|Awards=[[IEEE Donald O. Pederson Award in Solid-State Circuits]]; EDS Paul Rappaport Award; Commendation by the Minister of State for Science and Technology - Person of science and technological merits; National Invention Award - Prize of the Patent Attorney’s Association of Japan; National Medal of Honor with Purple Ribbon | |||
}} | |||
[[Image:Kiyoo Itoh 2278.jpg|thumb|right]] | |||
Hideo Sunami, Mitsumasa Koyanagi and Kiyoo Itoh are responsible for three of the major milestones in the evolution of modern dynamic random access memories (DRAMs). Their development of trench and stacked capacitor cells and folded data line cells resulted in unmatched high signal-to-noise ratio. Today, three decades after their invention, these cells remain the de facto standard for the DRAM industry. | [[Hideo Sunami]], [[Mitsumasa Koyanagi]] and Kiyoo Itoh are responsible for three of the major milestones in the evolution of modern dynamic random access memories (DRAMs). Their development of trench and stacked capacitor cells and folded data line cells resulted in unmatched high signal-to-noise ratio. Today, three decades after their invention, these cells remain the de facto standard for the DRAM industry. | ||
In 1974, Dr. Itoh conceived the concept of the folded data-line cell, which uses a pair of balanced data lines to eliminate various noise components. Since that time, this cell has been adopted for nearly all DRAM chips since produced. A Fellow at Hitachi, Ltd. in Tokyo, where he is responsible for all research and development, he has also developed key DRAM devices and circuits such as the triple-well structure, on-chip voltage down-converters and subthreshold-current reduction circuits. | In 1974, Dr. Itoh conceived the concept of the folded data-line cell, which uses a pair of balanced data lines to eliminate various noise components. Since that time, this cell has been adopted for nearly all DRAM chips since produced. A Fellow at Hitachi, Ltd. in Tokyo, where he is responsible for all research and development, he has also developed key DRAM devices and circuits such as the triple-well structure, on-chip voltage down-converters and subthreshold-current reduction circuits. | ||
An IEEE Fellow, Dr. Itoh has received the IEEE Solid State Circuits | An [[IEEE Fellow Grade History|IEEE Fellow]], Dr. Itoh has received the [[IEEE Donald O. Pederson Award in Solid-State Circuits]], the EDS Paul Rappaport Award, Commendation by the Minister of State for Science and Technology - Person of science and technological merits (Japan),the National Invention Award - Prize of the Patent Attorney’s Association of Japan, and the national Medal of Honor with Purple Ribbon (Japan). | ||
[[Category:Capacitors]] | |||
[[Category:Capacitors]] | |||
[[Category:Computing and electronics]] | |||
[[Category:Memory]] | [[Category:Memory]] | ||
{{DEFAULTSORT:Itoh}} | |||
Latest revision as of 16:38, 2 February 2016
- Fields of study
- Memory
- Awards
- IEEE Donald O. Pederson Award in Solid-State Circuits, EDS Paul Rappaport Award, Commendation by the Minister of State for Science and Technology - Person of science and technological merits, National Invention Award - Prize of the Patent Attorney’s Association of Japan, National Medal of Honor with Purple Ribbon
Biography
Hideo Sunami, Mitsumasa Koyanagi and Kiyoo Itoh are responsible for three of the major milestones in the evolution of modern dynamic random access memories (DRAMs). Their development of trench and stacked capacitor cells and folded data line cells resulted in unmatched high signal-to-noise ratio. Today, three decades after their invention, these cells remain the de facto standard for the DRAM industry.
In 1974, Dr. Itoh conceived the concept of the folded data-line cell, which uses a pair of balanced data lines to eliminate various noise components. Since that time, this cell has been adopted for nearly all DRAM chips since produced. A Fellow at Hitachi, Ltd. in Tokyo, where he is responsible for all research and development, he has also developed key DRAM devices and circuits such as the triple-well structure, on-chip voltage down-converters and subthreshold-current reduction circuits.
An IEEE Fellow, Dr. Itoh has received the IEEE Donald O. Pederson Award in Solid-State Circuits, the EDS Paul Rappaport Award, Commendation by the Minister of State for Science and Technology - Person of science and technological merits (Japan),the National Invention Award - Prize of the Patent Attorney’s Association of Japan, and the national Medal of Honor with Purple Ribbon (Japan).
