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Wen-Ben Jone

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<h2> Biography </h2>
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== Biography ==
<p>The next generation of integrated circuitry, featuring reconfigurability, selfrepair, fault-tolerance and self-manageability relies on chips that can effectively self-test. The paper "Fault Tolerant Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities," published in the December 2001 issue of IEEE Transactions on Instrumentation and Measurement by [[Sunil R. Das]], [[C.V. Ramamoorthy|Chittoor V. Ramamoorthy]], [[Mansour H. Assaf]], [[Emil M. Petriu]] and Wen-Ben Jone is a powerful reference for professionals who develop these new chips. The paper offers a lucid case for the importance of response data compaction, as well as an extensive overview of the various built-in self-test (BIST) methods available.
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</p><p>A Senior Member of the IEEE, Wen-Ben Jone is an associate professor in the Department of Electrical and Computer Engineering and Science at the University of Cincinnati in Ohio. His honors include the Best Thesis Award from the Chinese Institute of Electrical Engineering. His research interests include VLSI design for testability, BIST, memory testing, [[MEMS]] testing and repair, and low-power circuit design. He has published more than 100 papers and holds one patent.
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[[Category:Components,_circuits,_devices_&_systems]]
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The next generation of integrated circuitry, featuring reconfigurability, selfrepair, fault-tolerance and self-manageability relies on chips that can effectively self-test. The paper "Fault Tolerant Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities," published in the December 2001 issue of IEEE Transactions on Instrumentation and Measurement by [[Sunil R. Das]], [[C.V. Ramamoorthy|Chittoor V. Ramamoorthy]], [[Mansour H. Assaf]], [[Emil M. Petriu]] and Wen-Ben Jone is a powerful reference for professionals who develop these new chips. The paper offers a lucid case for the importance of response data compaction, as well as an extensive overview of the various built-in self-test (BIST) methods available.
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A Senior Member of the IEEE, Wen-Ben Jone is an associate professor in the Department of Electrical and Computer Engineering and Science at the University of Cincinnati in Ohio. His honors include the Best Thesis Award from the Chinese Institute of Electrical Engineering. His research interests include VLSI design for testability, BIST, memory testing, [[MEMS]] testing and repair, and low-power circuit design. He has published more than 100 papers and holds one patent.
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[[Category:Components, circuits, devices & systems|Bone]]

Revision as of 16:46, 6 March 2012

Biography

The next generation of integrated circuitry, featuring reconfigurability, selfrepair, fault-tolerance and self-manageability relies on chips that can effectively self-test. The paper "Fault Tolerant Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities," published in the December 2001 issue of IEEE Transactions on Instrumentation and Measurement by Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu and Wen-Ben Jone is a powerful reference for professionals who develop these new chips. The paper offers a lucid case for the importance of response data compaction, as well as an extensive overview of the various built-in self-test (BIST) methods available.

A Senior Member of the IEEE, Wen-Ben Jone is an associate professor in the Department of Electrical and Computer Engineering and Science at the University of Cincinnati in Ohio. His honors include the Best Thesis Award from the Chinese Institute of Electrical Engineering. His research interests include VLSI design for testability, BIST, memory testing, MEMS testing and repair, and low-power circuit design. He has published more than 100 papers and holds one patent.