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Robert S. Chau

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== Biography  ==
 
== Biography  ==
  
Mark T. Bohr, Robert S. Chau, and Tahir Ghani have played key leadership roles at Intel Corp. in developing the three biggest changes in transistor technology over the past decade. Their work has allowed the continued shrinking of transistor technology resulting in smaller, faster, and more energy-efficient microprocessors. The first revolutionary change in transistor technology was the team’s development of silicon germanium strained-silicon transistors, first described by Dr. Ghani in 2003. Applied in Intel’s 90-nm technology node, these transistors were the first material innovations implemented to improve transistor performance without increasing current leakage. This method improves electron and hole mobility in a transistor, providing faster on-off switching and resulting in faster microprocessors. Intel began volume production of the 90-nm transistors in 2003. The team’s second contribution to the continued scaling of chips was the high-k metal gate transistor that permitted scaling to the 45-nm generation. This technology overcame the performance and leakage limits presented by not being able to scale the gate dielectric in previous nodes. Intel replaced traditional silicon dioxide materials with a novel high-k dielectric and special metal gate electrode to achieve record-setting transistor performance with dramatically reduced current leakage. Intel began high-volume production of 45-nm microprocessors in 2007. The team’s third innovation was the tri-gate transistor featured in Intel’s 22-nm processors announced in 2011. Utilizing three sides of tall and narrow silicon fins to provide better gate control of current compared to traditional planar devices, these transistors provide significantly lower operating voltage, lower current leakage, and more “on state” current. This invention allows transistors that are smaller, faster, and use less power than ever before.
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[[Mark Bohr|Mark T. Bohr]], Robert S. Chau, and [[Tahir Ghani]] have played key leadership roles at Intel Corp. in developing the three biggest changes in transistor technology over the past decade. Their work has allowed the continued shrinking of transistor technology resulting in smaller, faster, and more energy-efficient microprocessors. The first revolutionary change in transistor technology was the team’s development of silicon germanium strained-silicon transistors, first described by Dr. Ghani in 2003. Applied in Intel’s 90-nm technology node, these transistors were the first material innovations implemented to improve transistor performance without increasing current leakage. This method improves electron and hole mobility in a transistor, providing faster on-off switching and resulting in faster microprocessors. Intel began volume production of the 90-nm transistors in 2003. The team’s second contribution to the continued scaling of chips was the high-k metal gate transistor that permitted scaling to the 45-nm generation. This technology overcame the performance and leakage limits presented by not being able to scale the gate dielectric in previous nodes. Intel replaced traditional silicon dioxide materials with a novel high-k dielectric and special metal gate electrode to achieve record-setting transistor performance with dramatically reduced current leakage. Intel began high-volume production of 45-nm microprocessors in 2007. The team’s third innovation was the tri-gate transistor featured in Intel’s 22-nm processors announced in 2011. Utilizing three sides of tall and narrow silicon fins to provide better gate control of current compared to traditional planar devices, these transistors provide significantly lower operating voltage, lower current leakage, and more “on state” current. This invention allows transistors that are smaller, faster, and use less power than ever before.
  
An IEEE Fellow, Dr. Chau is also a co-recepient of the 2012 [[IEEE Jun-ichi Nishizawa Medal]], awarded annually to those who have made "outstanding contributions to material and device science and technology, including practical application." Dr. Chau received this award, along with [[Mark Bohr|Mark T. Bohr]] and Tahir Ghani for "sustained leadership in developing innovative transistor technologies for advanced logic products.” Dr. Chau is currently an Intel Senior Fellow and director of transistor research and nanotechnology at Intel Corp., Hillsboro, Ore., where he has worked since 1989.
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An [[IEEE Fellow Grade History|IEEE Fellow]], Dr. Chau is also a co-recepient of the 2012 [[IEEE Jun-ichi Nishizawa Medal]], awarded annually to those who have made "outstanding contributions to material and device science and technology, including practical application." Dr. Chau received this award, along with Bohr and Ghani, for "sustained leadership in developing innovative transistor technologies for advanced logic products.” Dr. Chau is currently an Intel Senior Fellow and director of transistor research and nanotechnology at Intel Corp., Hillsboro, Ore., where he has worked since 1989.
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[[Category:Components,_circuits,_devices_&_systems]]
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[[Category:Solid_state_circuits]]
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[[Category:Transistors]]

Revision as of 14:04, 12 September 2013

Biography

Mark T. Bohr, Robert S. Chau, and Tahir Ghani have played key leadership roles at Intel Corp. in developing the three biggest changes in transistor technology over the past decade. Their work has allowed the continued shrinking of transistor technology resulting in smaller, faster, and more energy-efficient microprocessors. The first revolutionary change in transistor technology was the team’s development of silicon germanium strained-silicon transistors, first described by Dr. Ghani in 2003. Applied in Intel’s 90-nm technology node, these transistors were the first material innovations implemented to improve transistor performance without increasing current leakage. This method improves electron and hole mobility in a transistor, providing faster on-off switching and resulting in faster microprocessors. Intel began volume production of the 90-nm transistors in 2003. The team’s second contribution to the continued scaling of chips was the high-k metal gate transistor that permitted scaling to the 45-nm generation. This technology overcame the performance and leakage limits presented by not being able to scale the gate dielectric in previous nodes. Intel replaced traditional silicon dioxide materials with a novel high-k dielectric and special metal gate electrode to achieve record-setting transistor performance with dramatically reduced current leakage. Intel began high-volume production of 45-nm microprocessors in 2007. The team’s third innovation was the tri-gate transistor featured in Intel’s 22-nm processors announced in 2011. Utilizing three sides of tall and narrow silicon fins to provide better gate control of current compared to traditional planar devices, these transistors provide significantly lower operating voltage, lower current leakage, and more “on state” current. This invention allows transistors that are smaller, faster, and use less power than ever before.

An IEEE Fellow, Dr. Chau is also a co-recepient of the 2012 IEEE Jun-ichi Nishizawa Medal, awarded annually to those who have made "outstanding contributions to material and device science and technology, including practical application." Dr. Chau received this award, along with Bohr and Ghani, for "sustained leadership in developing innovative transistor technologies for advanced logic products.” Dr. Chau is currently an Intel Senior Fellow and director of transistor research and nanotechnology at Intel Corp., Hillsboro, Ore., where he has worked since 1989.