Milestone-Proposal:Whirlwind Computer: Difference between revisions
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3. IEEE Global History Network "Magnetic-Core Memory". | 3. IEEE Global History Network "Magnetic-Core Memory". | ||
http://www.ieeeghn.org/wiki/index.php/Magnetic-Core_Memory | http://www.ieeeghn.org/wiki/index.php/Magnetic-Core_Memory | ||
DESIGN AND CONSTRUCTION | DESIGN AND CONSTRUCTION | ||
By 1947, Forrester and collaborator Robert Everett [http://www.cs.stthomas.edu/faculty/resmith/papers/WhirlwindR-127.pdf completed the design] of a high-speed stored-program computer for this task. Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words. | By 1947, Forrester and collaborator Robert Everett [http://www.cs.stthomas.edu/faculty/resmith/papers/WhirlwindR-127.pdf completed the design] of a high-speed stored-program computer for this task. Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words. | ||
The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact | The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|a5=TECHNICAL DESCRIPTION | ||
By 1947, Forrester and collaborator Robert Everett completed the design of a high-speed stored-program computer. Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words. | By 1947, Forrester and collaborator Robert Everett completed the design of a high-speed stored-program computer. Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words. | ||
The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|a6=|a7=|a8= | The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|a6=|a7=|a8=Yes|a9=The building where Whirlwind was housed is located at 211 Massachusetts Avenue, Cambridge. The plaque would be readily visible to pedestrians walking on the public sidewalk along this major street in Cambridge.|a10=MIT|a11=Yes|a12=Boston Section with support by one or more Society Chapters.|a13name=Bruce Hecht|a13section=Boston|a13position=2010 Chair|a13email=Bruce.Hecht@analog.com|a14name=Robert Alongi|a14ou=Boston Section|a14position=Section Business Manager|a14email=sec.boston@ieee.org|a15Aname=Gilmore Cooke|a15Aemail=gilcooke@ieee.org|a15Aname2=|a15Aemail2=|a15Bname=c/o Robert Alongi|a15Bemail=sec.boston@ieee.org|a15Bname2=|a15Bemail2=|a15Cname=Gilmore Cooke|a15Ctitle=PE retired|a15Corg=Boston Section Committee|a15Caddress=8 Canvasback, W Yarmouth MA 02673|a15Cphone=617-759-4271|a15Cemail=gilcooke@ieee.org}} |
Revision as of 17:30, 6 December 2010
This Proposal has not been submitted and may only be edited by the original author.