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First-Hand:Solid State Circuits Society First Hand Histories

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The [[IEEE Solid-State Circuits Society History|IEEE Solid-State Circuits Society]] has, since the beginning of its Newsletter in 2006 (it became a Magazine in 2009), featured articles on history. Many of these are “first-hand histories” of the sort featured on the IEEE Global History Network. Therefore, the IEEE Global History Network has partnered with the IEEE Solid-State Systems Society to make those particularly articles free to the public on IEEE Xplore, which is IEEE’s digital library that delivers access to the world's highest quality technical literature in engineering and technology. The abstracts and links for the Solid-State Systems collection appear below.
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The [[IEEE Solid-State Circuits Society History|IEEE Solid-State Circuits Society]] has, since the beginning of its Newsletter in 2006 (it became a Magazine in 2009), featured articles on history. Many of these are “first-hand histories” of the sort featured on the IEEE Global History Network. Therefore, the IEEE Global History Network has partnered with the IEEE Solid-State Circuits Society to make those particularly articles free to the public on IEEE Xplore, which is IEEE’s digital library that delivers access to the world's highest quality technical literature in engineering and technology. The abstracts and links for the Solid-State Circuits collection appear below.  
  
 
Dale L. Critchlow<br> Winter 2007, pp. 19-22<br> [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4785536 Recollections on MOSFET Scaling]<br> In mid-1970, [[Robert H. Dennard|Bob Dennard]], Fritz Gaensslen and Larry Kuhn formalized the constant-field scaling theory and its limitations. Bob Dennard went on to contribute profoundly to the demonstration of the feasibility of MOSFET scaling and led the way into implementation in real products. Scaled CMOS has become the dominant technology for digital and many analog applications and will continue to be a fundamental driving force of the industry for years to come.  
 
Dale L. Critchlow<br> Winter 2007, pp. 19-22<br> [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4785536 Recollections on MOSFET Scaling]<br> In mid-1970, [[Robert H. Dennard|Bob Dennard]], Fritz Gaensslen and Larry Kuhn formalized the constant-field scaling theory and its limitations. Bob Dennard went on to contribute profoundly to the demonstration of the feasibility of MOSFET scaling and led the way into implementation in real products. Scaled CMOS has become the dominant technology for digital and many analog applications and will continue to be a fundamental driving force of the industry for years to come.  
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Alberto Sangiovanni-Vincentelli<br> Summer 2010, pp. 6-25:<br> [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5545707 Corsi e Ricorsi: The EDA Story]<br> I dedicate this article to the memory of electronic design automation (EDA) pioneers [[Donald O. Pederson|Don Pederson]] and Richard Newton (see “Don Pederson and Richard Newton, EDA Pioneers”), who are no longer with us, and to the many friends, colleagues, and students with whom I had the great pleasure to work.  
 
Alberto Sangiovanni-Vincentelli<br> Summer 2010, pp. 6-25:<br> [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5545707 Corsi e Ricorsi: The EDA Story]<br> I dedicate this article to the memory of electronic design automation (EDA) pioneers [[Donald O. Pederson|Don Pederson]] and Richard Newton (see “Don Pederson and Richard Newton, EDA Pioneers”), who are no longer with us, and to the many friends, colleagues, and students with whom I had the great pleasure to work.  
  
Robert Brayton<br>
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Robert Brayton<br> Summer 2010, pp 26-31 <br> [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5545679 Summer of '81]<br> On 1981, the idea that one could synthesize logic automatically from an RTL description into an implementation of gates and flip-flops was not new. At IBM, there were already several efforts under way at that time, and there had been earlier efforts in the same direction by Se June Hong, John Paul Roth, and others. Roth had written a program that was used to create a logic network from an RTL description. There was no attempt to optimize the network, possibly because it was thought to be too hard to compete with manual implementations. This program was mainly used to create a golden model for comparison with handcrafted logic, which was the mode of implementation at the time. There was a companion program, called SAS at IBM, which was used to do the checking. It was a fairly universal rule at IBM that before any logic was released in a product, one should “SAS” it. This program was basically an early version of a SAT solver and was remarkably capable for the time. It was finally published in the IBM Journal of Research and Development, but for a long time this program was not documented except in the IBM Technical Disclosure Bulletin. In 1974, Hong and Ostapko had created an early programmable logic array (PLA) minimization program, MINI, which used some very innovative ideas and was the leading PLA minimization program. Of course, in the early 1960s, Quine and McCluskey had the first ideas on minimization of sum-of-product expressions (SOPs).  
Summer 2010, pp 26-31 <br>
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[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5545679 Summer of '81]<br>
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On 1981, the idea that one could synthesize logic automatically from an RTL description into an implementation of gates and flip-flops was not new. At IBM, there were already several efforts under way at that time, and there had been earlier efforts in the same direction by Se June Hong, John Paul Roth, and others. Roth had written a program that was used to create a logic network from an RTL description. There was no attempt to optimize the network, possibly because it was thought to be too hard to compete with manual implementations. This program was mainly used to create a golden model for comparison with handcrafted logic, which was the mode of implementation at the time. There was a companion program, called SAS at IBM, which was used to do the checking. It was a fairly universal rule at IBM that before any logic was released in a product, one should “SAS” it. This program was basically an early version of a SAT solver and was remarkably capable for the time. It was finally published in the IBM Journal of Research and Development, but for a long time this program was not documented except in the IBM Technical Disclosure Bulletin. In 1974, Hong and Ostapko had created an early programmable logic array (PLA) minimization program, MINI, which used some very innovative ideas and was the leading PLA minimization program. Of course, in the early 1960s, Quine and McCluskey had the first ideas on minimization of sum-of-product expressions (SOPs).  
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[[Category:Components,_circuits,_devices_&_systems|{{PAGENAME}}]] [[Category:Solid_state_circuits|{{PAGENAME}}]] [[Category:Computers_and_information_processing|{{PAGENAME}}]] [[Category:Computer_science|{{PAGENAME}}]]
 
[[Category:Components,_circuits,_devices_&_systems|{{PAGENAME}}]] [[Category:Solid_state_circuits|{{PAGENAME}}]] [[Category:Computers_and_information_processing|{{PAGENAME}}]] [[Category:Computer_science|{{PAGENAME}}]]

Revision as of 20:37, 5 January 2011

The IEEE Solid-State Circuits Society has, since the beginning of its Newsletter in 2006 (it became a Magazine in 2009), featured articles on history. Many of these are “first-hand histories” of the sort featured on the IEEE Global History Network. Therefore, the IEEE Global History Network has partnered with the IEEE Solid-State Circuits Society to make those particularly articles free to the public on IEEE Xplore, which is IEEE’s digital library that delivers access to the world's highest quality technical literature in engineering and technology. The abstracts and links for the Solid-State Circuits collection appear below.

Dale L. Critchlow
Winter 2007, pp. 19-22
Recollections on MOSFET Scaling
In mid-1970, Bob Dennard, Fritz Gaensslen and Larry Kuhn formalized the constant-field scaling theory and its limitations. Bob Dennard went on to contribute profoundly to the demonstration of the feasibility of MOSFET scaling and led the way into implementation in real products. Scaled CMOS has become the dominant technology for digital and many analog applications and will continue to be a fundamental driving force of the industry for years to come.

Gene M. Amdahl
Summer 2007, pp. 4-9
Computer Architecture and Amdahl's Law
In this thumbnail autobiography, Dr. Amdahl describes his early career, beginning with a serendipitous programming assignment as a graduate student in physics at the University of Wisconsin in 1950 and culminating in the formulation of "Amdahl's Law" in 1967.

Barrie Gilbert
Fall 2007, pp.10-28
The Gears of Genius
A self-described "lone wolf-cub, befriended only by a hyperactive urge to experiment with everything," Barrie Gilbert recalls his coming of age in the nascent world of analog circuit design and his emergence as an inventor and author of papers that have become classics in the field.

Robert H. Dennard
Winter 2008, pp. 10-16
Revisiting Evolution of the MOSFET Dynamic RAM - A Personal View
This first-person account of the early days of semiconductor memory development explains how Dr. Robert Dennard's invention of DRAM came about and chronicles the evolution of DRAM technology from 1967 through 1984. In that period, he reports, there was a lot of circuit and architectural innovation in a very competitive environment, with little documentation in the public literature.

Mitsumasa Koyanagi
Winter 2008, pp. 37-41
The Stacked Capacitor DRAM Cell and Three-Dimensional Memory
The key component in a stored-program-type computer is memory, the repository for data and instructions. In this article Dr. Mitsumasa Koyanagi chronicles the development of the stacked three-dimensional (3D) DRAM cell, highlighting his role in solving the problems of memory data-bandwidth and forecasting a dramatic increase in memory capacity based on his current work using "super-chip" integration technology.

Eric A. Vittoz
Summer 2008, pp. 7-23
The Electronic Watch and Low-Power Circuits
Renowned as an expert in low-power CMOS circuit design and for groundbreaking work with miniature electronic devices, Dr. Eric A. Vittoz relates his life, work and times in this original retrospective for the SSCS News. According to Yannis Tsividis, also in this issue, Dr. Vittoz's influence continues to grow, as low voltage and low power become increasingly important in the engineering of mobile devices. Dr. Vittoz is a Research Fellow at the Swiss Center for Electronics and Microtechnology in Neuchatel, Switzerland, an IEEE Fellow, and a professor at EPFL, the Ecole Polytechnique Federale de Lausanne. He has published more than 130 papers and holds 26 patents

Christian Enz
Summer 2008, pp.24-30
A Short Story of the EKV MOS Transistor Model
The EKV MOS transistor model and design methodology evolved from the first weak inversion transistor models of the 1970's. In this first-hand account, Christian Enz chronicles the evolution of the hierarchical structure, limited parameters and flexibility of the EKV model that he developed with colleagues such as Francois Krummenacher and Eric Vittoz (the "E" "K" and "V" of EKV) at the Centre Electronique Horloger (CEH) in Neuchatel. With the aggressive downscaling of CMOS technologies today, the EKV compact model is shifting increasingly from the traditional strong inversion region toward moderate and weak inversion regions.

Gordon Bell
Fall 2008, pp.8-19
Bell's Law for the Birth and Death of Computer Classes: A theory of the Computer's Evolution
In 1951 a man could walk inside a computer. By 2010, a computer cluster with millions of processors will have expanded to building size. In this new paper Gordon Bell explains the history of the computing industry, positing a general theory ("Bell's Law") for the creation, evolution, and death of computer classes since 1951. Using the exponential transistor density increases forecast by Moore's Law in 1965 and 1975 as the principal basis for the life cycle of computer classes after the microprocessor was introduced in 1971, he predicts that the powerful microprocessor will be the basis for nearly all computer classes in 2010, from personal computers and servers costing a few thousand dollars to scalable servers costing a few hundred million dollars. Soon afterward, billions of cell phones for personal computing, and tens of billions of wireless sensor nets will unwire and interconnect everything.

Erik H. M. Heijne
Fall 2008, pp. 28-34
Gigasensors for an Attoscope: Catching Quanta in CMOS
Around 1987, Eric Vittoz studied the basic parameters for the development of 'pixel' particle tracking detectors in collaboration with a team in Geneva at CERN. CERN scientist Erik Heijne traces the evolution of these particle imagers, which has resulted in matrices of 256x256 pixels with > 1000 transistors per pixel that can process single quanta and have connections with neighboring cells allowing analog and logic operations at ns time-scale for distrbiuted events.

Federico Fagin
Winter 2009, pp. 8-21
The Making of the First Microprocessor
The paper discusses the making of the first microprocessor and its history of how it is made. The Intel 4004 CPU-on-a-chip was developed under pressure on an extremely tight schedule.

Marcian E. Hoff
Winter 2009, pp. 22-28
Designing the First Microprocessor
We now routinely buy personal computers in which microprocessors with millions of transistors perform at gigahertz speeds, so it is easy to forget that the first microprocessor was not a simple or obvious choice to produce. At the time it was being contemplated, metal oxide semiconductor (MOS) technology was still quite new, and integrated circuits themselves had existed less than a decade. While MOS circuits with a thousand transistors were being manufactured, the economics of integrated circuits of that day limited how far the technology could be pushed. The paper discusses how rethinking a customer's specifications led to simplifications that made the first microprocessor possible.

Stanley Mazor
Winter 2009, pp. 29-38
Moore's Law, Microcomputers, and Me
In 1960--ten years before Intel developed the first single-chip CPU (microcomputer central processing unit)-the revolution that would ensue was inconceivable: the cost of computing dropped by a factor of a million, modes of personal communication changed forever, and intelligent machines took over processes in manufacturing, transportation, medicine-virtually every aspect of our lives. Certainly Moore's law - that the number of transistors on a chip doubles every year, later amended to every two years - is a dominant factor in this revolution. In this paper, the author gives his views on Moore's law and focus on the role of applications engineering in developing Intel's first microcomputer.

Masatoshi Shima
Winter 2009, pp. 39-45
The 4004 CPU of My Youth - Developing the world's first microprocessor
This article is a recollection of the development of the world's first microprocessor, the 4004, as seen from Busicom Corp., the Japanese desktop calculator manufacturer where this author was working from the late 1960s to the early 1970s. In 1969, Busicom Corp. launched a project to develop LSI chips for a ROM-based, macroinstruction-programmable decimal computer system. At that time, Busicom was a successful Japanese manufacturer of electronic calculators with a reputation for innovation. Through the LSI project, Busicom and Intel Corporation succeeded in March 1971 in developing the world's first 4-b microprocessor, the 4004, a product that was conceptually the exclusive property of Busicom.

Joseph A. Fisher
Spring 2009, pp. 10-27
VLIW Processors: From Blue Sky to Best Buy
Very long instruction word (VLIW) is an architectural style that one of the authors-Josh Fisher-proposed about 30 years ago to speed up computers and otherwise enhance their performance. Those listening to Fisher's first public "blue-sky" expositions of this technology in the early 1980s did not generally expect it to succeed. Indeed, they would have been stunned to hear of the success these processors are enjoying today, especially as embedded processors, designed to perform special-purpose functions, usually in real time, in some kind of hardware. VLIWs obtain high performance from ordinary programs in a way that is simple to describe: Instead of issuing a single operation from an instruction stream in a given cycle, a VLIW processor issues many of them together in a single execution stream, and it issues new operations before old ones have finished.

Robert P. Colwell
Spring 2009, pp. 18-22
VLIW: The Unlikeliest Computer Architecture
The computer architecture community of the late 1970s and early 1980s thought that a few things had been established and no longer needed questioning. One of these was the amount of intrinsic parallelism embedded in normal object code. Making what they considered to be self-evident assumptions about correctness, Tjaden and Flynn established that there was, on average, only a factor of two parallelism available. Breakthroughs often come from people who somehow transcend the assumptions and have the guts to follow the newly revealed path wherever it leads. This phenomenon first hand with Josh Fisher's VLIW work.

Ken Smith
Fall 2009, pp. 8-17
The Story Behind Microelectronic Circuits
The author's 1982 text, coauthored jointly with Adel Sedra, has sold over 1 million copies. This article describes how this book came to be and the genesis of products such as the iPhone.

Tom Rent
Winter 2010, pp. 14-20
Rent's Rule: A Family Memoir
IEEE Solid-State Circuits readers are fortunate. In mid-October 2008, my 82-yearold father received a request from the IEEE to prepare an article on Rent's rule that would be featured in the Winter 2010 issue. The IEEE didn't know at the time that my father, Edward Francis Rent, died unexpectedly at home on 3 October 2008, seemingly from a stroke. Had my father received this IEEE request prior to his death, he would have politely turned it down. He was not one to celebrate his brilliance or draw attention to himself, ever. He simply lived for the benefit of others.

John W. Meredith
Spring 2010, pp. 10-16
The Soul of a New Chip: An IC Designer describes how his first custom MOS LSI device was built and tested at AMI
This paper describes how an IC design engineer got his first custom MOS LSI device was built and tested at American Microsystems Incorporated (AMI), circa 1972.

Alberto Sangiovanni-Vincentelli
Summer 2010, pp. 6-25:
Corsi e Ricorsi: The EDA Story
I dedicate this article to the memory of electronic design automation (EDA) pioneers Don Pederson and Richard Newton (see “Don Pederson and Richard Newton, EDA Pioneers”), who are no longer with us, and to the many friends, colleagues, and students with whom I had the great pleasure to work.

Robert Brayton
Summer 2010, pp 26-31
Summer of '81
On 1981, the idea that one could synthesize logic automatically from an RTL description into an implementation of gates and flip-flops was not new. At IBM, there were already several efforts under way at that time, and there had been earlier efforts in the same direction by Se June Hong, John Paul Roth, and others. Roth had written a program that was used to create a logic network from an RTL description. There was no attempt to optimize the network, possibly because it was thought to be too hard to compete with manual implementations. This program was mainly used to create a golden model for comparison with handcrafted logic, which was the mode of implementation at the time. There was a companion program, called SAS at IBM, which was used to do the checking. It was a fairly universal rule at IBM that before any logic was released in a product, one should “SAS” it. This program was basically an early version of a SAT solver and was remarkably capable for the time. It was finally published in the IBM Journal of Research and Development, but for a long time this program was not documented except in the IBM Technical Disclosure Bulletin. In 1974, Hong and Ostapko had created an early programmable logic array (PLA) minimization program, MINI, which used some very innovative ideas and was the leading PLA minimization program. Of course, in the early 1960s, Quine and McCluskey had the first ideas on minimization of sum-of-product expressions (SOPs).