First-Hand:Cryo CMOS and 40+ layer PC Boards - How Crazy is this?
How it started
It was in the early 80's. Control Data (CDC) had launched the CYBER - 205 with modest success and the team was now focused on the next generation machine, the 2XX as I recall. Speed, cost and meeting the schedule were all key objectives. Speed because Cray Research under the guidance of Seymour Cray was setting milestones for Supercomputers with the Cray 1 and then the Cray 2. Cost, since Supercomputers were extremely expensive. Schedules since the CYBER - 205 had established patience records as a machine that may never get out the door and this must not be repeated.
A conventional evolutionary approach for Integrated Circuit (IC) logic was initially selected. Motorola, with some prodding, agreed to launch an 8,000 gate equivalent ECL (emitter-coupled-logic - the circuitry of choice for high performance processing units) provided Control Data do the development. There were insufficient customers for Motorola to commit their resources to this lofty development. They did, however, commit their advanced ECL processes to CDC and a joint team was developed with the two companies.
Logic designers at the CDC Advanced Design Laboratory were given preliminary design rules based on computer device models and estimates of gate per chip densities. There was a natural follow up of grumbling but circuit designers had learned to accept this since logic designers always found the circuits to be too slow and insufficient in quantity per die. There was a lot of cooperation too. Basic building blocks were defined by the logic designers - gate functionality, register functionality, etc. From this set of preliminary rules function blocks were defined and capacity per reasonably-sized Printed Circuit (PC) boards and initial design using the Cray CYBER - 205 based architecture was launched.
In parallel with this effort, and in the same circuit, packaging, PC board and newly formed CAD (tools for layout and design of chips and boards), chief chip design engineer - Randy Bach - was assigned to develop an advanced CMOS chip for the Canadian Computer Development organization. At this time, early 80's CMOS was in it's infancy being used for memory devices, low performance peripherals and also for low performance microprocessors. The design contained 5,000 gates plus appropriate input and output communication devices. Gate arrays for CMOS was also nearly non-existent so Randy and his small team of two assistants developed a cell library and worked closely with the Canadian Development team to meet their objectives as well. This effort was completely separate from the ECL based gate array to be used for the next generation Supercomputer. The product was a cost driven - low cost application driven effort.
It was customary for Neil Lincoln - chief architect - Dale Handy - manufacturing manager and me to go off to lunch every 8 to 10 days to discuss status at either Author Treacher's Fish & Chips or Zantigo's (high class - NOT - fast food restaurants). As a side note, both of these fast food places disappeared during the ETA Systems brief duration - Neil often thought we were the cause. Zantigo's has returned (I think because they know it is safe now that the three of us cannot visit together any longer - Neil unfortunately left us a few years ago).
On one of these meetings, Neil had "news" for me. The gate array in co-development with Motorola was not sufficient for his goals. He had determined that the CPU (some 3 Million gates) had to be put on a single board. "It was time for this to be done". He also felt that the logic design required at least 15,000 gates per chip to meet the goals. The logic designers had gotten to him I surmised. Schedules, of course, could not be altered - and that was that. To soften the blow he bought lunch that day, three Cokes and three orders of fish and chips - Neil's was a large order.
The trip back to the lab was pretty quiet, fortunately short since our eating places were all very close to the lab.
