First-Hand:Cryo CMOS and 40+ layer PC Boards - How Crazy is this?

How it started

It was in the early 80's.  Control Data (CDC) had launched the CYBER - 205 with modest success and the team was now focused on the next generation machine, the 2XX as I recall.  Speed, cost and meeting the schedule were all key objectives.  Speed because Cray Research under the guidance of Seymour Cray was setting the milestones.  Cost, since Supercomputers were extremely expensive.  Schedules since the CYBER - 205 had established as a machine that may never get out the door and this just could not be repeated.

A conventional evolutionary approach for Integrated Circuit (IC) logic was selected.  Motorola, with some prodding, agreed to launch an 8,000 gate equivalent ECL (emitter-coupled-logic - the circuitry of choice for high performance processing units) provided Control Data do the development.  There were insufficient customers for Motorola to commit their resources to this lofty development.  They did, however, commit their advanced ECL processes to CDC and a joint team was developed with the two companies.  

Logic designers at the CDC Advanced Design Laboratory were given preliminary design rules based on computer models and estimates of gate per chip densities.  From this function blocks were defined and capacity per reasonably-sized Printed Circuit (PC) boards and initial design using the Cray CYBER - 205 based architecture was launched.

In parallel with this effort, Randy Bach was assigned to develop an advanced CMOS chip for the Canadian Development organization.  At this time, early 80's CMOS was in it's infancy being used for memory devices, low performance peripherals and also for low performance microprocessors.  The design contained 5,000 gates plus appropriate input and output communication devices.  Gate arrays for CMOS was also nearly non-existent so Randy and his small team of two assistants developed a cell library and worked closely with the Canadian Development team to meet their objectives as well.  This effort was completely separate from the ECL based gate array to be used for the next generation Supercomputer.  It was a cost driven low cost application driven effort.