Considered one of the top integrated-circuit researchers in the world, Takayasu Sakurai’s contributions to CMOS technology have enabled the scaling down of chip sizes needed for today’s handheld electronics. Dr. Sakurai was one of the earliest researchers to create solutions to power problems facing CMOS logic circuit designers. His simplified models provide designers with intuition of chip performance that is needed to use circuit simulation tools effectively. The “Sakurai model,” developed in 1991, was the world’s first realistic interconnect delay and capacitance model formula and plays a key role in developing today’s high-speed circuits. His “alpha power law model” has been used in many tools for estimating how transistor performance will scale with technology to optimize size and at the same time minimize power.
An IEEE Fellow, Dr. Sakurai is currently a professor with the University of Tokyo’s Institute of Industrial Science.